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| MC100LVELT22 3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator The MC100LVELT22 is a dual LVTTL/LVCMOS to differential LVPECL translator. Because LVPECL (Low Voltage Positive ECL) levels are used, only +3.3 V and ground are required. The small outline 8-lead package and the low skew, dual gate design of the LVELT22 makes it ideal for applications which require the translation of a clock and a data signal. http://onsemi.com MARKING DIAGRAMS* 8 8 1 SO-8 D SUFFIX CASE 751 1 8 8 1 TSSOP-8 DT SUFFIX CASE 948R 1 A L Y W = Assembly Location = Wafer Lot = Year = Work Week KR22 ALYW KVT22 ALYW * * * * * * 350 ps Typical Propagation Delay <100 ps Output-to-Output Skew ESD Protection: >4 KV HBM, >200 V MM Flow Through Pinouts The 100 Series Contains Temperature Compensation LVPECL Operating Range: VCC= 3.0 V to 3.8 V with GND= 0 V When Unused TTL Input is left Open, Q Output will Default High * * Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test * Moisture Sensitivity Level 1 * Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34 For Additional Information, see Application Note AND8003/D *For additional information, see Application Note AND8002/D * Transistor Count = 164 devices ORDERING INFORMATION Device MC100LVELT22D MC100LVELT22DR2 MC100LVELT22DT Package SO-8 SO-8 TSSOP-8 Shipping 98 Units / Rail 2500 / Reel 98 Units / Rail 2500 / Reel MC100LVELT22DTR2 TSSOP-8 (c) Semiconductor Components Industries, LLC, 2000 1 October, 2000 - Rev. 1 Publication Order Number: MC100LVELT22/D MC100LVELT22 Q0 1 8 VCC PIN DESCRIPTION Q0 2 LVPECL LVTTL/ LVCMOS 7 D0 PIN Qn, Qn D0, D1 VCC GND FUNCTION LVPECL Differential Outputs LVTTL/LVCMOS Inputs Positive Supply Ground Q1 3 6 D1 Q1 4 5 GND Figure 1. 8-Lead Pinout (Top View) and Logic Diagram MAXIMUM RATINGS (Note 1.) Symbol VCC VI Iout TA Tstg JA JC JA JC Tsol Parameter Positive Power Supply Input Voltage Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Wave Solder 0 LFPM 500 LFPM std bd 0 LFPM 500 LFPM std bd <2 to 3 sec @ 248C 8 SOIC 8 SOIC 8 SOIC 8 TSSOP 8 TSSOP 8 TSSOP Condition 1 GND = 0 V GND = 0 V Continuous Surge VI VCC Condition 2 Rating 7 7 50 100 -40 to +85 -65 to +150 190 130 41 to 44 5% 185 140 41 to 44 5% 265 Units V V mA mA C C C/W C/W C/W C/W C/W C/W C 1. Maximum Ratings are those values beyond which device damage may occur. http://onsemi.com 2 MC100LVELT22 LVPECL DC CHARACTERISTICS VCC= 3.3 V; GND= 0.0 V (Note 1.) -40C Symbol ICC VOH VOL Characteristic Power Supply Current Output HIGH Voltage (Note 2.) Output LOW Voltage (Note 2.) 2275 1490 Min Typ Max 28 2420 1680 2275 1490 Min 25C Typ Max 28 2420 1680 2275 1490 Min 85C Typ Max 29 2420 1680 Unit mA mV mV NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. Output parameters vary 1:1 with VCC. VCC can vary 0.15V. 2. Outputs are terminated through a 50 ohm resistor to VCC-2 volts. LVTTL/LVCMOS INPUT DC CHARACTERISTICS VCC = 3.3V; TA = -40C to 85C (Note 1.) Symbol IIH IIHH IIL VIK VIH VIL Input HIGH Voltage Input LOW Voltage 2.0 0.8 Characteristic Input HIGH Current Input HIGH Current Input LOW Current Min Typ Max 20 100 -0.2 -1.2 Unit A A mA V V V Condition VIN = 2.7V VIN = VCC VIN = 0.5V IIN = -18mA 1. VCC can vary 0.15V. AC CHARACTERISTICS VCC= 3.3 V; GND= 0.0 V (Note 1.) -40C Symbol fmax t t PLH skew 25C Max Min Typ TBD 600 100 400 200 350 30 TBD 550 200 500 200 600 100 400 200 Max Min 85C Typ TBD 350 30 TBD 500 600 100 400 Max Unit GHz ps ps ps ps Characteristic Maximum Toggle Frequency Propagation Delay (Note 2.) Skew Cycle-to-Cycle Jitter Output Rise/Fall Time (20-80%) Output-to-Output Part-to-Part Min Typ TBD 200 350 30 TBD tJITTER t /t rf 200 1. VCC can vary 0.15 V. 2. Specifications for standard TTL input signal. http://onsemi.com 3 MC100LVELT22 Q Driver Device Qb 50 W 50 W D Receiver Device Db V TT V TT = V CC - 2.0 V Figure 1. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020 - Termination of ECL Logic Devices.) Resource Reference of Application Notes AN1404 - ECLinPS Circuit Performance at Non-Standard VIH Levels AN1405 AN1406 AN1503 AN1504 AN1560 AN1568 AN1596 AN1650 AN1672 AND8001 AND8002 AND8020 - - - - - - - - - - - - ECL Clock Distribution Techniques Designing with PECL (ECL at +5.0 V) ECLinPS I/O SPICE Modeling Kit Metastability and the ECLinPS Family Low Voltage ECLinPS SPICE Modeling Kit Interfacing Between LVDS and ECL ECLinPS Lite Translator ELT Family SPICE I/O Model Kit Using Wire-OR Ties in ECLinPS Designs The ECL Translator Guide Odd Number Counters Design Marking and Date Codes Termination of ECL Logic Devices http://onsemi.com 4 MC100LVELT22 PACKAGE DIMENSIONS SO-8 D SUFFIX PLASTIC SOIC PACKAGE CASE 751-07 ISSUE V A 8 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D G H J K M N S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244 -X- B 1 4 S 0.25 (0.010) M Y M -Y- G C -Z- H D 0.25 (0.010) M SEATING PLANE K N X 45 _ 0.10 (0.004) M J ZY S X S http://onsemi.com 5 MC100LVELT22 PACKAGE DIMENSIONS TSSOP-8 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948R-02 ISSUE A 8x K REF 0.10 (0.004) M 0.15 (0.006) T U S 2X TU S V S L/2 8 5 L 1 PIN 1 IDENT 4 B -U- 0.25 (0.010) M 0.15 (0.006) T U S A -V- F DETAIL E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 2.90 3.10 2.90 3.10 0.80 1.10 0.05 0.15 0.40 0.70 0.65 BSC 0.25 0.40 4.90 BSC 0_ 6_ INCHES MIN MAX 0.114 0.122 0.114 0.122 0.031 0.043 0.002 0.006 0.016 0.028 0.026 BSC 0.010 0.016 0.193 BSC 0_ 6_ C 0.10 (0.004) -T- SEATING PLANE D -W- G DETAIL E DIM A B C D F G K L M http://onsemi.com 6 MC100LVELT22 Notes http://onsemi.com 7 MC100LVELT22 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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